Sequential Circuit Test Generation Using Dynamic State

A new method for state justiication is proposed for sequential circuit test generation. The linear list of states dynamically obtained during the derivation of test vectors is used to guide the search during state justiication. State-transfer sequences may already be known that drive the circuit from the current state to the target state. Otherwise, genetic engineering of existing state-transfer sequences is required. In both cases, genetic-algorithm-based techniques are used to generate valid state justiication sequences for the circuit in the presence of the target fault. This approach achieves extremely high fault coverages and thus out-performs previous deterministic and simulation-based techniques. The majority of the time spent by automatic test generators for sequential circuits is used to nd test sequences for hard-to-test faults. Deterministic test generators have been proposed in the past, but they often require backtracing through complex gates and ip-ops, and remodeling of such primitives is often required. In addition, large numbers of backtracks are often needed for the hard faults. Simulation-based test generators , on the other hand, avoid the complexity of backtracing by processing in the forward direction only. However, previous simulation-based approaches often fell short when targeting the hard faults because they lacked information about state justiication. Previously, homing, synchronizing, and distinguishing sequences have been used to aid the test generator in improving the fault coverage 1, 2, 3, 4, 5]. In 1, 2, 4], symbolic and state-table-based techniques were used to derive these sequences in the fault-free machine. Speciically, in 1], cube intersections of ON/OFF-set representations were used to derive distinguishing sequences. Binary decision diagrams (BDD's) and implicit state enumeration were used in 2] to derive synchronizing sequences. In the work by Park et al., 4], functional information was used to pre-generate sequences which sim-pliied propagation of fault eeects from the ip-ops to the primary outputs (PO's), and state justiication was done by using BDD's. Since these sequences are generated using the fault-free machine only, they may become invalid in a faulty machine. Homing sequences composed of specifying and distinguishing portions were used to aid ATPG in 3], but they had to be recomputed for each target fault. Several approaches to test generation using genetic algorithms (GA's) have been proposed in the past 5-14]. Fitness functions were used to guide the GA in nding a test vector or sequence that maximizes given objectives for a single fault or group of faults. However, hard-to-test faults often …